TSMC OIP Ecosystem Forum

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	TSMC Technical Sessions
11:20 – 11:50	TSMC Talk: Synergizing TSMC Angstrom-Scale Technology and AI Computing: Accelerating Silicon and Design Cycle TSMC	TSMC Talk: Taming AI System Design Complexity: Methodology Innovations for Next-Generation 3DIC TSMC
	Advanced Logic & 3D IC Track	Analog, RF, Specialty Track
11:50 – 13:00	Lunch & Ecosystem Pavilion
13:00 – 13:20	Standardizing Wafer-level HVM PIC testing Using V93000-Triton Photonics Solution Advantest / Formfactor	Accelerate Floorplanning and Rapid Layout Editing with Custom Compiler Smart Floorplanning Synopsys / Mediatek
13:20 – 13:40	Scaling AI Data Center’s Infrastructure: Protocol Agnostic Physical Design for Scale-Up using 224G SerDes Alchip Technologies / Synopsys	PCI Express Solutions for HPC/AI Storage: Benefiting from TSMC’s advanced processes Cadence Design Systems / SK hynix
13:40 – 14:00	Scaling up AI Compute, Memory and Connectivity GUC	A Scalable PDN Optimization Methodology for Adaptive Multi-Package Automotive MCUs Synopsys / NXP Semiconductors
14:00 – 14:20	Accelerating Physical Verification with Agentic AI DRC Fixing Siemens EDA / Google	Breaking the I/O Bottleneck: A Silicon-Proven 4nm M-PHY G5 with Leakage-Optimized Design for High-Bandwidth AI Data Streaming M31 Technology
14:20 – 14:40	Automated Architecture-Phase PDN Prototyping Workflow to Advance Multi-Die Designs Synopsys / Mediatek	Driving Next Gen Memory Interfaces: LPDDR6/5X combo subsystem for High Bandwidth, Low Latency with Optimum Data Traffic with CPU/GPU/XPU, in Applications such as AI, Cyber security, Datacenter, and Automotive Innosilicon / Axiado
14:40 – 15:00	Coffee Break & Ecosystem Pavilion
15:00 – 15:20	COUPE‑Enabled Co‑Packaged Optics through ASIC and Photonic Interconnect Co‑Design Alphawave Semi / Lightmatter	AI-Powered RF Design Migration Flow for Transition from TSMC’s N6RF+ to N4P Process Node Keysight Technolgies / Synopsys
15:20 – 15:40	Multiphysics‑Aware Timing Signoff and Design Closure for AI and HPC Designs Synopsys / Nvidia	M31 ultra-low power foundation IP solution on TSMC N12e Platform: Powering Edge AI and IoT applications M31 Technology / Ambiq Micro
15:40 – 16:00	A Robust EDA Framework for Silicon Photonic Design Integration: Connectivity and Signoff in PDIE Cadence Design Systems	Accelerating AI SoC Time-to-Market: NeoFuse OTP as the Silicon-Proven Anchor for PVT Calibration, Memory Repair, and Caliptra-Compliant Root-of-Trust eMemory / ASPEED Technology
16:00 – 16:20	Methodology for Fmax-per-Watt Scaling in CPU-Centric Designs Using Advanced EDA and DTCO Techniques Synopsys / Qualcomm Technologies	Reliability-Aware Analog Design Optimization Cadence Design Systems
16:20 – 16:40	Efficient, scalable methodology for reliability and ESD verification of complex 3D IC CoWoS systems Siemens EDA / Marvell	From Cloud to Physical AI: Edge SoCs on TSMC ‘C’ Nodes Powered by UFS, LPDDR and Die-to-Die Synopsys / Synopsys
16:40 – 17:00	Lucky Draw

Advanced Logic & 3D IC Track	Analog, RF, Specialty Track
ATPG Solutions for Small-delay Defects -- Path-Delay vs Timing-Aware Siemens EDA / AMD	Catching SOA Violations in Over-Voltage-Tolerant (OVT) GPIOs on Advanced FinFET Nodes Sofics / Siemens EDA
An Innovative IR-ECO Technique Enabling Fast Design Convergence for High-End SoC Synopsys / Sanechips
A Novel Algorithm-Based Approach to Accelerating IR-STA Flow Synopsys / NXP Semiconductors
A Distributed and Scalable Dynamic Power Integrity Flow from Early Analysis to Sign-off for Large-Scale SerDes Designs Synopsys / Sanechips Technology
Transforming DRC from a Static Run to an Intelligent, Agentic Experience with Calibre and Fuse AI Siemens EDA
Trust but Verify: Microsoft's IP Validation Methodology Across Design Views and Revisions on TSMC 3nm Siemens EDA / Microsoft
Bridging the Thermal Divide: Empowering ASIC Designers with an Automated Model Generation Toolbox for Thermal-Aware Design HCL Technologies / A semiconductor organization in power and image sensing products
PFSC ESD full chip and 3DIC successful usage Synopsys
How Tempus™ PDK Timing Prediction Achieves Timing Signoff Accuracy on TSMC N2P Cadence Design Systems / Broadcom
Taping out multi-billion-gate, advanced process node SoC with IC Validator Synopsys / Nvidia
Backside Methodology for AI/HPC on TSMC A16/A12 using Synopsys Fusion Compiler Synopsys
Next-Gen Verification: Overcoming ERC and SOFTCHK Challenges for Faster Design Iterations Siemens EDA / SanDisk
From Design to Mass Production: GUC and FuriosaAI’s Joint Collaboration on RNGD GUC / FuriosaAI
From C4 to Hybrid in Photonic Integrated Circuit: Routing-Centric Constraints for Power/Ground in 3D-Integrated Platforms Synopsys
Simulate of TSMC COUPE Optical I/O Chip-to-Fiber Coupling System by Keysight's Optical Tools Keysight Technolgies, Inc. / Keysight Technoligies / Keysight Technoligies
Warpage Simulation Fitting, Stress Simulation Method and Glass Core Substrate Application of Advanced Package for AI Chips Synopsys / Iluvatar CoreX
Enhancing Thermal Aware Optimization for 3D Heterogeneous Chiplets Integration: A System- Technology Co-Optimization (STCO) Perspective on Spatial-Temporal Temperature Uniformity Synopsys / Witmem
EMIR Signoff Methodology and Novel Models for Custom HBM Synopsys / Synopsys / Synopsys
Enabling AI-Optimized Memory Subsystems with LPDDR6/5X and SOCAMM-Based Architectures Cadence Design Systems / Cadence Design Systems
Synopsys–GUC Ecosystem for Optical I/O in 3DIC CPO Architectures Synopsys / GUC
Addressing Inter-Die STA Complexity for 3D Multi-Die Designs Synopsys / Arm
Demonstrating Synopsys Lane Test & Repair on TSMC Light IOs for Vertical 3DIC Solutions Synopsys / TSMC