|
Time
|
Plenary Session
|
| 08:30 - 09:30 |
Registration & Ecosystem Pavilion |
| 09:30 - 09:40 |
Welcome Remarks |
| 09:40 - 10:00 |
TSMC Keynote |
| 10:00 - 10:20 |
Guest Speech |
| 10:20 - 10:50 |
TSMC Keynote |
| 10:50 – 11:20 |
Coffee Break & Ecosystem Pavilion |
|
TSMC Technical Sessions |
| 11:20 – 11:50 |
TSMC Talk: Synergizing TSMC Angstrom-Scale Technology and AI Computing: Accelerating Silicon and Design Cycle
TSMC
|
TSMC Talk: Taming AI System Design Complexity: Methodology Innovations for Next-Generation 3DIC
TSMC
|
|
OIP Partner Technical Talks |
|
Advanced Logic & 3D IC Track |
Analog, RF, Specialty Track |
| 11:50 – 13:00 |
Lunch & Ecosystem Pavilion |
| 13:00 – 13:20 |
Standardizing Wafer-level HVM PIC testing Using V93000-Triton Photonics Solution
Advantest / Formfactor
|
Accelerate Floorplanning and Rapid Layout Editing with Custom Compiler Smart Floorplanning
Synopsys / Mediatek
|
| 13:20 – 13:40 |
Scaling AI Data Center’s Infrastructure: Protocol Agnostic Physical Design for Scale-Up using 224G SerDes
Alchip Technologies / Synopsys
|
PCI Express Solutions for HPC/AI Storage: Benefiting from TSMC’s advanced processes
Cadence Design Systems / SK hynix
|
| 13:40 – 14:00 |
Scaling up AI Compute, Memory and Connectivity
GUC
|
A Scalable PDN Optimization Methodology for Adaptive Multi-Package Automotive MCUs
Synopsys / NXP Semiconductors
|
| 14:00 – 14:20 |
Accelerating Physical Verification with Agentic AI DRC Fixing
Siemens EDA / Google
|
Breaking the I/O Bottleneck: A Silicon-Proven 4nm M-PHY G5 with Leakage-Optimized Design for High-Bandwidth AI Data Streaming
M31 Technology
|
| 14:20 – 14:40 |
Automated Architecture-Phase PDN Prototyping Workflow to Advance Multi-Die Designs
Synopsys / Mediatek
|
Driving Next Gen Memory Interfaces: LPDDR6/5X combo subsystem for High Bandwidth, Low Latency with Optimum Data Traffic with CPU/GPU/XPU, in Applications such as AI, Cyber security, Datacenter, and Automotive
Innosilicon / Axiado
|
| 14:40 – 15:00 |
Coffee Break & Ecosystem Pavilion |
| 15:00 – 15:20 |
COUPE‑Enabled Co‑Packaged Optics through ASIC and Photonic Interconnect Co‑Design
Alphawave Semi / Lightmatter
|
AI-Powered RF Design Migration Flow for Transition from TSMC’s N6RF+ to N4P Process Node
Keysight Technolgies / Synopsys
|
| 15:20 – 15:40 |
Multiphysics‑Aware Timing Signoff and Design Closure for AI and HPC Designs
Synopsys / Nvidia
|
M31 ultra-low power foundation IP solution on TSMC N12e Platform: Powering Edge AI and IoT applications
M31 Technology / Ambiq Micro
|
| 15:40 – 16:00 |
A Robust EDA Framework for Silicon Photonic Design Integration: Connectivity and Signoff in PDIE
Cadence Design Systems
|
Accelerating AI SoC Time-to-Market: NeoFuse OTP as the Silicon-Proven Anchor for PVT Calibration, Memory Repair, and Caliptra-Compliant Root-of-Trust
eMemory / ASPEED Technology
|
| 16:00 – 16:20 |
Methodology for Fmax-per-Watt Scaling in CPU-Centric Designs Using Advanced EDA and DTCO Techniques
Synopsys / Qualcomm Technologies
|
Reliability-Aware Analog Design Optimization
Cadence Design Systems
|
| 16:20 – 16:40 |
Efficient, scalable methodology for reliability and ESD verification of complex 3D IC CoWoS systems
Siemens EDA / Marvell
|
From Cloud to Physical AI: Edge SoCs on TSMC ‘C’ Nodes Powered by UFS, LPDDR and Die-to-Die
Synopsys / Synopsys
|
| 16:40 – 17:00 |
Lucky Draw |
