TSMC OIP Ecosystem Forum

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	TSMC Technical Sessions
11:30 – 12:00	TSMC Talk: Advanced Node Design TSMC	TSMC Talk: 3D IC Design TSMC	TSMC Talk: Scaling AI with Leadership Silicon and Cohesive System Optimization TSMC
	Advanced Logic Track	3D IC Track	Analog, RF, Specialty Track
12:00 – 12:20	Nvidia Advanced Node AI Accelerator Implementation using Cadence Digital Full Flow Cadence Design Systems / Nvidia	Addressing Inter-Die STA Complexity for 3D Multi-Die Designs Synopsys / Arm	On-Die Power Management for Scalable SoCs and Chiplet Architectures Analog Bits / Cerebras
12:20 – 13:30	Lunch & Ecosystem Pavilion
13:30 – 13:50	Multiphysics‑Aware Timing Signoff and Design Closure for AI and HPC Designs Synopsys / Nvidia	3DIC package level ESD verification using Calibre 3DPERC Siemens EDA / AMD	Integrated Pre- and Postlayout Circuit Optimization Flow on TSMC N3 using Cadence Virtuoso Studio Cadence Design Systems / Nvidia
13:50 – 14:10	AI-Enabled Optimization of Arm’s Highest-Performance CPU on TSMC's Advanced Node Cadence Design Systems / ARM	Scaling AI Data Center’s Infrastructure: Protocol Agnostic Physical Design for Scale-Up using 224G SerDes Alchip Technologies / Synopsys	IBIS-AMI Based Modeling Approach for Forwarded Clocking Architecture in End-to-end UCIe System Simulation Keysight Technolgies / Qualcomm
14:10 – 14:30	Accelerating Physical Verification with Agentic AI DRC Fixing Siemens EDA / Google	Broadcom 3DIC STA Signoff with Tempus Cadence Design Systems / Broadcom	Large-scale Chip-Level 3D EM Extraction and Sign-off of Ultra-High-Speed Silicon Photonics and Custom Silicon IC/3DIC Designs with PeakView Lorentz Solution / Nvidia
14:30 – 14:50	Delivering complex TSMC N2P AI chips for Microsoft datacenter deployment Cadence Design Systems / Microsoft	Scaling up AI Compute, Memory and Connectivity GUC	M31 ultra-low power foundation IP solution on TSMC N12e Platform: Powering Edge AI and IoT applications M31 Technology / Ambiq Micro
14:50 – 15:10	Methodology for Fmax-per-Watt Scaling in CPU-Centric Designs Using Advanced EDA and DTCO Techniques Synopsys / Qualcomm Technologies	LPDDR6 and UCIe interface routing automation and optimization use cases using ASR Cadence Design Systems / Socionext	Ensuring reliability in advanced TSMC nodes: catching SOA violations in over-voltage-tolerant GPIOs from Sofics IP using the Siemens EDA flow Sofics / Siemens EDA
15:10 – 15:30	Coffee Break & Ecosystem Pavilion
15:30 – 15:50	Identifying Weakest Links: A Cell Scoring Metric for Robust Design in Advanced Nodes Siemens EDA / NXP	Designing with CoWoS S, CoWoS R and CoWoS L: package technology selection and co design for next generation heterogeneous systems. IMEC	PCI Express Solutions for HPC/AI Storage: Benefiting from TSMC’s advanced processes Cadence Design Systems / SK hynix
15:50 – 16:10	Automated architecture-phase PDN prototyping workflow Synopsys / Mediatek	224G PAM4 and 64G NRZ TIA and Driver IP in TSMC N3P for COUPE-Based Co-Packaged Optics Omni Design Technologies	Accelerating AI SoC Time-to-Market: NeoFuse OTP as the Silicon-Proven Anchor for PVT Calibration, Memory Repair, and Caliptra-Compliant Root-of-Trust eMemory / Arm / ASPEED Technology
16:10 – 16:30	PDK-Ready in Hours, Not Weeks: How Tempus™ Timing Solution’s Silicon Prediction Achieves Timing Signoff Accuracy on TSMC 3FFE and 2GAAP Cadence Design Systems / Broadcom	From Signal to Thermal: Where HBM Innovation Goes Next Samsung Memory	LPDDR Memory: Enabling Power-Efficient Performance in AI, Automotive and Data Center Systems Rambus
16:30 – 16:50	University Talk Ⅰ TSMC	University Talk Ⅱ TSMC	University Talk Ⅲ TSMC
16:50 – 18:00	Networking and Reception

Advanced Logic Track	3D IC Track	Analog, RF, Specialty Track
Sigma Profiling: Profiling Solution for Power Integrity Signoff Synopsys / Nvidia	A Robust EDA Framework for Silicon Photonic Design Integration: Connectivity and Signoff in PDIE Cadence Design Systems	High-speed wireline data converters for beyond 100GBaud links in 5 and 3nm IMEC
Closing the RTL-to-Silicon Loop: An Agentic AI Flywheel for Deep RTL Analysis, Partition Exploration, and Physically-Aware Synthesis on TSMC N3 Cadence Design Systems	Warpage Simulation Fitting, Stress Simulation Method and Glass Core Substrate Application of Advanced Package for AI Chips Synopsys / Iluvatar CoreX	Improving Timing Margin Confidence Through Fast Monte Carlo Statistical Expansion Cadence Design Systems / Lattice Semiconductor
Deploying Super AI Agents to accelerate TSMC advanced node tapeout Cadence Design Systems	Wafer-level HVM PIC testing using V93000-Triton Photonics Solution Advantest / Nvidia / Formfactor	AI-Powered RF Design Migration Flow for Transition from TSMC’s N6RF+ to N4P Process Node Keysight Technolgies / Synopsys
A Distributed and Scalable Dynamic Power Integrity Flow from Early Analysis to Sign-off for Large-Scale SerDes Designs Synopsys / Sanechips Technology	Reference Flow for IVR Stucture: Multi-Die EM/IR, Thermal, and System-Level PI Analysis with Integrated IVR Modeling Synopsys	Datacenter-Scale CPU Power Management using Integrated Power and Clocking in N3/N2 SoCs Analog Bits / Arm
Machine‑Learning‑driven PVT Generation and Correlation Analysis of Standard Cell Libraries Siemens EDA / Altera Corporation	Efficient, scalable methodology for reliability and ESD verification of complex 3D IC CoWoS systems Siemens EDA / Marvell	Pinless PLL and PVT Sensor IP for Automotive SoCs in Advanced FinFET Nodes Analog Bits / Socionext
An Innovative IR-ECO Technique Enabling Fast Design Convergence for High-End SoC Synopsys / Sanechips	Speeding up CoWoS Interposer Routing with Cadence OmniRoute and AI based SI Optimization Cadence Design Systems	A Scalable PDN Optimization Methodology for Adaptive Multi-Package Automotive MCUs Synopsys / NXP Semiconductors
PFSC ESD full chip and 3DIC successful usage Synopsys	From Design to Mass Production: GUC and FuriosaAI’s Joint Collaboration on RNGD GUC / FuriosaAI	AI-Accelerated Surrogate Modeling for Rapid RFIC/MMIC Design Validation Keysight Technolgies
Taping out multi-billion-gate, advanced process node SoC with IC Validator Synopsys / Nvidia	Cadence 3DStack AI Super Agent for TSMC 3DFabric: Agentic AI Generation of 3Dblox Files and Rapid Bring Up of Early EM/IR/Thermal & System Level LVS Cadence Design Systems	Reliability-Aware Analog Design Optimization Cadence Design Systems
Transforming DRC from a Static Run to an Intelligent, Agentic Experience with Calibre and Fuse AI Siemens EDA	Demonstrating Synopsys Lane Test & Repair on TSMC Light IOs for Vertical 3DIC Solutions Synopsys / TSMC	Leveraging Cloud-Scale Infrastructure to Accelerate Silicon Tape-Outs using ARM core Graviton processors. Siemens EDA / Amazon
A Novel Algorithm-Based Approach to Accelerating IR-STA Flow Synopsys / NXP Semiconductors	Hierarchical design planning and verification for CoWoS-L technology: an incremental methodology Siemens EDA / ARM
ATPG Solutions for Small-delay Defects -- Path-Delay vs Timing-Aware Siemens EDA / AMD	Package-Level Thermal Characterization Using Vapor Chamber Lid for High-Power AI/Datacenter Applications STATS ChipPAC
	Comprehensive die-to-system thermal management solutions for advanced 3D IC packaging Siemens EDA / Asperitas
	Streamlining TSMC 3DFabric™ Assembly Verification Siemens EDA / Broadcom
	COUPE‑Enabled Co‑Packaged Optics through ASIC and Photonic Interconnect Co‑Design Alphawave Semi / Lightmatter
	Shift-Left Quality Screening for Chiplet-Based Architectures Using Telemetry-Based Analytics proteanTecs / Amkor Technology