Agenda：Online Event

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Join the 2026 TSMC Open Innovation Platform Ecosystem Forum and learn from OIP partners how to leverage their technology for your design challenges!

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Date: Tuesday, October 6, 2026

Plenary Session
Welcome & Ecosystem Pavilion
Opening Remarks
TSMC Keynote Ⅰ
Guest Speech
TSMC Keynote Ⅱ

Included All In-Person Papers

Advanced Logic Track

Sigma Profiling: Profiling Solution for Power Integrity Signoff

Synopsys / Nvidia

Closing the RTL-to-Silicon Loop: An Agentic AI Flywheel for Deep RTL Analysis, Partition Exploration, and Physically-Aware Synthesis on TSMC N3

Cadence Design Systems

Deploying Super AI Agents to accelerate TSMC advanced node tapeout

Cadence Design Systems

A Distributed and Scalable Dynamic Power Integrity Flow from Early Analysis to Sign-off for Large-Scale SerDes Designs

Synopsys / Sanechips Technology

Machine‑Learning‑driven PVT Generation and Correlation Analysis of Standard Cell Libraries

Siemens EDA / Altera Corporation

An Innovative IR-ECO Technique Enabling Fast Design Convergence for High-End SoC

Synopsys / Sanechips

PFSC ESD full chip and 3DIC successful usage

Synopsys

Taping out multi-billion-gate, advanced process node SoC with IC Validator

Synopsys / Nvidia

Transforming DRC from a Static Run to an Intelligent, Agentic Experience with Calibre and Fuse AI

Siemens EDA

A Novel Algorithm-Based Approach to Accelerating IR-STA Flow

Synopsys / NXP Semiconductors

ATPG Solutions for Small-delay Defects -- Path-Delay vs Timing-Aware

Siemens EDA / AMD
3D IC Track

A Robust EDA Framework for Silicon Photonic Design Integration: Connectivity and Signoff in PDIE

Cadence Design Systems

Warpage Simulation Fitting, Stress Simulation Method and Glass Core Substrate Application of Advanced Package for AI Chips

Synopsys / Iluvatar CoreX

Wafer-level HVM PIC testing using V93000-Triton Photonics Solution

Advantest / Nvidia / Formfactor

Reference Flow for IVR Stucture: Multi-Die EM/IR, Thermal, and System-Level PI Analysis with Integrated IVR Modeling

Synopsys

Efficient, scalable methodology for reliability and ESD verification of complex 3D IC CoWoS systems

Siemens EDA / Marvell

Speeding up CoWoS Interposer Routing with Cadence OmniRoute and AI based SI Optimization

Cadence Design Systems

From Design to Mass Production: GUC and FuriosaAI’s Joint Collaboration on RNGD

GUC / FuriosaAI

Cadence 3DStack AI Super Agent for TSMC 3DFabric: Agentic AI Generation of 3Dblox Files and Rapid Bring Up of Early EM/IR/Thermal & System Level LVS

Cadence Design Systems

Demonstrating Synopsys Lane Test & Repair on TSMC Light IOs for Vertical 3DIC Solutions

Synopsys / TSMC

Hierarchical design planning and verification for CoWoS-L technology: an incremental methodology

Siemens EDA / ARM

Package-Level Thermal Characterization Using Vapor Chamber Lid for High-Power AI/Datacenter Applications

STATS ChipPAC

Comprehensive die-to-system thermal management solutions for advanced 3D IC packaging

Siemens EDA / Asperitas

Streamlining TSMC 3DFabric™ Assembly Verification

Siemens EDA / Broadcom

COUPE‑Enabled Co‑Packaged Optics through ASIC and Photonic Interconnect Co‑Design

Alphawave Semi / Lightmatter

Shift-Left Quality Screening for Chiplet-Based Architectures Using Telemetry-Based Analytics

proteanTecs / Amkor Technology
Analog, RF, Specialty Track

High-speed wireline data converters for beyond 100GBaud links in 5 and 3nm

IMEC

Improving Timing Margin Confidence Through Fast Monte Carlo Statistical Expansion

Cadence Design Systems / Lattice Semiconductor

AI-Powered RF Design Migration Flow for Transition from TSMC’s N6RF+ to N4P Process Node

Keysight Technolgies / Synopsys

Datacenter-Scale CPU Power Management using Integrated Power and Clocking in N3/N2 SoCs

Analog Bits / Arm

Pinless PLL and PVT Sensor IP for Automotive SoCs in Advanced FinFET Nodes

Analog Bits / Socionext

A Scalable PDN Optimization Methodology for Adaptive Multi-Package Automotive MCUs

Synopsys / NXP Semiconductors

AI-Accelerated Surrogate Modeling for Rapid RFIC/MMIC Design Validation

Keysight Technolgies

Reliability-Aware Analog Design Optimization

Cadence Design Systems

Leveraging Cloud-Scale Infrastructure to Accelerate Silicon Tape-Outs using ARM core Graviton processors.

Siemens EDA / Amazon

*The agenda is subject to change by TSMC.

Legal Notice

TSMC is not responsible for the content, accuracy, or reliability of any of the presentations at the TSMC Open Innovation Platform Ecosystem Forum. Furthermore, posting the presentation abstracts on TSMC's corporate website does not constitute an endorsement of the content of those presentations by TSMC. Any liability arising from the contents of any of the presentations is the responsibility of the presenter itself, and not TSMC.

The views expressed in the presentations made at this event are those of the speaker and are not necessarily those of TSMC.