|
Time
|
Plenary Session
|
| 08:30 - 09:30 |
Registration & Ecosystem Pavilion |
| 09:30 - 09:40 |
Welcome Remarks |
| 09:40 - 10:00 |
TSMC Keynote Ⅰ |
| 10:00 - 10:30 |
Guest Speech |
| 10:30 - 11:00 |
TSMC Keynote ⅠⅠ |
| 11:00 – 11:30 |
Coffee Break & Ecosystem Pavilion |
|
TSMC Technical Sessions |
| 11:30 – 12:00 |
TSMC Talk: Advanced Node Design
TSMC
|
TSMC Talk: 3D IC Design
TSMC
|
TSMC Talk: Scaling AI with Leadership Silicon and Cohesive System Optimization
TSMC
|
|
OIP Partner Technical Sessions |
|
Advanced Logic Track |
3D IC Track |
Analog, RF, Specialty Track |
| 12:00 – 12:20 |
Nvidia Advanced Node AI Accelerator Implementation using Cadence Digital Full Flow
Cadence Design Systems / Nvidia
|
Addressing Inter-Die STA Complexity for 3D Multi-Die Designs
Synopsys / Arm
|
On-Die Power Management for Scalable SoCs and Chiplet Architectures
Analog Bits / Cerebras
|
| 12:20 – 13:30 |
Lunch & Ecosystem Pavilion |
| 13:30 – 13:50 |
Multiphysics‑Aware Timing Signoff and Design Closure for AI and HPC Designs
Synopsys / Nvidia
|
3DIC package level ESD verification using Calibre 3DPERC
Siemens EDA / AMD
|
Integrated Pre- and Postlayout Circuit Optimization Flow on TSMC N3 using Cadence Virtuoso Studio
Cadence Design Systems / Nvidia
|
| 13:50 – 14:10 |
AI-Enabled Optimization of Arm’s Highest-Performance CPU on TSMC's Advanced Node
Cadence Design Systems / ARM
|
Scaling AI Data Center’s Infrastructure: Protocol Agnostic Physical Design for Scale-Up using 224G SerDes
Alchip Technologies / Synopsys
|
IBIS-AMI Based Modeling Approach for Forwarded Clocking Architecture in End-to-end UCIe System Simulation
Keysight Technolgies / Qualcomm
|
| 14:10 – 14:30 |
Accelerating Physical Verification with Agentic AI DRC Fixing
Siemens EDA / Google
|
Broadcom 3DIC STA Signoff with Tempus
Cadence Design Systems / Broadcom
|
Large-scale Chip-Level 3D EM Extraction and Sign-off of Ultra-High-Speed Silicon Photonics and Custom Silicon IC/3DIC Designs with PeakView
Lorentz Solution / Nvidia
|
| 14:30 – 14:50 |
Delivering complex TSMC N2P AI chips for Microsoft datacenter deployment
Cadence Design Systems / Microsoft
|
Scaling up AI Compute, Memory and Connectivity
GUC
|
M31 ultra-low power foundation IP solution on TSMC N12e Platform: Powering Edge AI and IoT applications
M31 Technology / Ambiq Micro
|
| 14:50 – 15:10 |
Methodology for Fmax-per-Watt Scaling in CPU-Centric Designs Using Advanced EDA and DTCO Techniques
Synopsys / Qualcomm Technologies
|
LPDDR6 and UCIe interface routing automation and optimization use cases using ASR
Cadence Design Systems / Socionext
|
Ensuring reliability in advanced TSMC nodes: catching SOA violations in over-voltage-tolerant GPIOs from Sofics IP using the Siemens EDA flow
Sofics / Siemens EDA
|
| 15:10 – 15:30 |
Coffee Break & Ecosystem Pavilion |
| 15:30 – 15:50 |
Identifying Weakest Links: A Cell Scoring Metric for Robust Design in Advanced Nodes
Siemens EDA / NXP
|
Designing with CoWoS S, CoWoS R and CoWoS L: package technology selection and co design for next generation heterogeneous systems.
IMEC
|
PCI Express Solutions for HPC/AI Storage: Benefiting from TSMC’s advanced processes
Cadence Design Systems / SK hynix
|
| 15:50 – 16:10 |
Automated architecture-phase PDN prototyping workflow
Synopsys / Mediatek
|
224G PAM4 and 64G NRZ TIA and Driver IP in TSMC N3P for COUPE-Based Co-Packaged Optics
Omni Design Technologies
|
Accelerating AI SoC Time-to-Market: NeoFuse OTP as the Silicon-Proven Anchor for PVT Calibration, Memory Repair, and Caliptra-Compliant Root-of-Trust
eMemory / Arm / ASPEED Technology
|
| 16:10 – 16:30 |
PDK-Ready in Hours, Not Weeks: How Tempus™ Timing Solution’s Silicon Prediction Achieves Timing Signoff Accuracy on TSMC 3FFE and 2GAAP
Cadence Design Systems / Broadcom
|
From Signal to Thermal: Where HBM Innovation Goes Next
Samsung Memory
|
LPDDR Memory: Enabling Power-Efficient Performance in AI, Automotive and Data Center Systems
Rambus
|
| 16:30 – 16:50 |
University Talk Ⅰ
TSMC
|
University Talk Ⅱ
TSMC
|
University Talk Ⅲ
TSMC
|
| 16:50 – 18:00 |
Networking and Reception |
