Agenda：Online Event

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Join the TSMC 2026 Japan Open Innovation Platform Ecosystem Workshop and learn from OIP partners how to leverage their technology for your design challenges!

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Date: Thursday, November 19, 2026

Plenary Session
Welcome & Ecosystem Pavilion
Opening Remarks
TSMC Keynote Ⅰ
Guest Speech
TSMC Keynote Ⅱ

Included All In-Person Papers

Advanced Logic & 3D IC Track

An Innovative IR-ECO Technique Enabling Fast Design Convergence for High-End SoC

Synopsys / Sanechips

PFSC ESD full chip and 3DIC successful usage

Synopsys

Taping out multi-billion-gate, advanced process node SoC with IC Validator

Synopsys / Nvidia

Transforming DRC from a Static Run to an Intelligent, Agentic Experience with Calibre and Fuse AI

Siemens EDA

A Novel Algorithm-Based Approach to Accelerating IR-STA Flow

Synopsys / NXP Semiconductors

How Tempus™ PDK Timing Prediction Achieves Timing Signoff Accuracy on TSMC N2P

Cadence Design Systems / Broadcom

ATPG Solutions for Small-delay Defects -- Path-Delay vs Timing-Aware

Siemens EDA / AMD

Warpage Simulation Fitting, Stress Simulation Method and Glass Core Substrate Application of Advanced Package for AI Chips

Synopsys / Iluvatar CoreX

Addressing Inter-Die STA Complexity for 3D Multi-Die Designs

Synopsys / Arm

Standardizing Wafer-level HVM PIC testing Using V93000-Triton Photonics Solution

Advantest / Formfactor

Reference Flow for IVR Stucture: Multi-Die EM/IR, Thermal, and System-Level PI Analysis with Integrated IVR Modeling

Synopsys

COUPE‑Enabled Co‑Packaged Optics through ASIC and Photonic Interconnect Co‑Design

Alphawave Semi / Lightmatter

AI Agent Driven Pre-Layout Optimization of Chiplet Interconnect Structures

Keysight Technolgies, Inc. / D&V / D&V

Enabling AI-Optimized Memory Subsystems with LPDDR6/5X and SOCAMM-Based Architectures

Cadence Design Systems / Cadence Design Systems
Analog, RF, Specialty Track

M31 ultra-low power foundation IP solution on TSMC N12e Platform: Powering Edge AI and IoT applications

M31 Technology / Ambiq Micro

From Cloud to Physical AI: Edge SoCs on TSMC ‘C’ Nodes Powered by UFS, LPDDR and Die-to-Die

Synopsys / Synopsys

Accelerating AI SoC Time-to-Market: NeoFuse OTP as the Silicon-Proven Anchor for PVT Calibration, Memory Repair, and Caliptra-Compliant Root-of-Trust

eMemory / ASPEED Technology

Integrating Chiptop ESD into Digital Standard Cell Libraries

Certus Semiconductor / SRF Technologies / Siemens EDA

Breaking the I/O Bottleneck: A Silicon-Proven 4nm M-PHY G5 with Leakage-Optimized Design for High-Bandwidth AI Data Streaming

M31 Technology

TCAD‑Assisted Model Calibration for Reliable SPICE Simulation Across Extreme Temperature Regimes

HCL Technologies / Automotive component supplier and large OEMs

Robust PHY Clocking: Silicon Creations in partnership with Synopsys

Silicon Creations / General / Synopsys Inc.

Mitigating OTP Data Leakage Risks in Advanced SoCs Through Secure Storage Architectures

Synopsys

Power-Scalable Multi-Rate eUSB2V2 PHY IP in TSMC N2P

M31 Technology

Demonstrating Synopsys Lane Test & Repair on TSMC Light IOs for Vertical 3DIC Solutions

Synopsys / TSMC

*The agenda is subject to change by TSMC.

Legal Notice

TSMC is not responsible for the content, accuracy, or reliability of any of the presentations at the TSMC Open Innovation Platform Ecosystem Workshop. Furthermore, posting the presentation abstracts on TSMC's corporate website does not constitute an endorsement of the content of those presentations by TSMC. Any liability arising from the contents of any of the presentations is the responsibility of the presenter itself, and not TSMC.

The views expressed in the presentations made at this event are those of the speaker and are not necessarily those of TSMC.