|
Time
|
Plenary Session
|
| 08:30 - 09:30 |
Registration & Ecosystem Pavilion |
| 09:30 - 09:40 |
Welcome Remarks |
| 09:40 - 10:00 |
Guest Speech |
| 10:00 - 10:15 |
TSMC Keynote I |
| 10:15 - 10:40 |
TSMC Keynote II |
| 10:40 – 11:00 |
Coffee Break & Ecosystem Pavilion |
|
TSMC Technical Talks |
| 11:00 – 11:30 |
TSMC
|
TSMC
|
|
OIP Partner Technical Sessions |
|
Advanced Logic & 3D IC Track |
Analog, RF, Specialty Track |
| 11:00 – 11:25 |
Scaling AI Data Center’s Infrastructure: Protocol Agnostic Physical Design for Scale-Up using 224G SerDes
Alchip Technologies / Synopsys
|
Reliability-Aware Analog Design Optimization
Cadence Design Systems
|
| 11:25 – 11:50 |
Scaling up AI Compute, Memory and Connectivity
GUC
|
PCI Express Solutions for HPC/AI Storage: Benefiting from TSMC’s advanced processes
Cadence Design Systems / SK hynix
|
| 11:50 – 12:15 |
Methodology for Fmax-per-Watt Scaling in CPU-Centric Designs Using Advanced EDA and DTCO Techniques
Synopsys / Qualcomm Technologies
|
AI-Powered RF Design Migration Flow for Transition from TSMC’s N6RF+ to N4P Process Node
Keysight Technolgies / Synopsys
|
| 12:15 – 13:00 |
Lunch & Ecosystem Pavilion |
| 13:00 – 13:25 |
A Distributed and Scalable Dynamic Power Integrity Flow from Early Analysis to Sign-off for Large-Scale SerDes Designs
Synopsys / Sanechips Technology
|
Production-Quality Memory IP Signoff at Scale: A NXP and Siemens EDA Joint Deployment of Solido IP Validation Suite on TSMC Automotive Nodes
Siemens EDA / NXP Semiconductors
|
| 13:25 – 13:50 |
From Design to Mass Production: GUC and FuriosaAI’s Joint Collaboration on RNGD
GUC / FuriosaAI
|
Driving Next Gen Memory Interfaces: LPDDR6/5X combo subsystem for High Bandwidth, Low Latency with Optimum Data Traffic with CPU/GPU/XPU, in Applications such as AI, Cyber security, Datacenter, and Automotive
Innosilicon / Axiado
|
| 13:50 – 14:15 |
A Scalable PDN Optimization Methodology for Adaptive Multi-Package Automotive MCUs
Synopsys / NXP Semiconductors
|
Accelerate Floorplanning and Rapid Layout Editing with Custom Compiler Smart Floorplanning
Synopsys / Mediatek
|
| 14:15 – 14:40 |
Liberty-Based Profiling for IP Benchmarking
Siemens EDA / NXP
|
Catching SOA Violations in Over-Voltage-Tolerant (OVT) GPIOs on Advanced FinFET Nodes
Sofics / Siemens EDA
|
| 14:40 – 15:00 |
Automated Architecture-Phase PDN Prototyping Workflow to Advance Multi-Die Designs
Synopsys / Mediatek
|
TSMC 22ULL MRAM for Automotive MCU Applications
tsmc / Semidrive
|
| 15:00 – 15:30 |
Coffee Break & Ecosystem Pavilion |
| 15:30 – 17:30 |
Tutorial Ⅰ: Advanced Node Digital Flow & Intro to 3DFabric
TSMC
|
Tutorial Ⅱ: Analog/RF Design & Migration
TSMC
|
| 17:30 – 18:30 |
Closing Reception & Raffle |
