TSMC OIP Ecosystem Forum

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	TSMC Technical Sessions
11:30 - 12:00	TSMC Talk: Synergizing TSMC Angstrom-Scale Technology and AI Computing: Accelerating Silicon and Design Cycle TSMC	TSMC Talk: Scaling AI with Leadership Silicon and Cohesive System Optimization TSMC
	Advanced Logic & 3D IC Track	Analog, RF, Specialty Track
12:00 - 12:20	Scaling AI Data Center’s Infrastructure: Protocol Agnostic Physical Design for Scale-Up using 224G SerDes Alchip Technologies / Synopsys	AI-Accelerated Surrogate Modeling for Rapid RFIC/MMIC Design Validation Keysight Technolgies
12:20 – 13:30	Lunch & Ecosystem Pavilion
13:30 – 13:50	ATPG Solutions for Small-delay Defects -- Path-Delay vs Timing-Aware Siemens EDA / AMD	Driving Next Gen Memory Interfaces: LPDDR6/5X combo subsystem for High Bandwidth, Low Latency with Optimum Data Traffic with CPU/GPU/XPU, in Applications such as AI, Cyber security, Datacenter, and Automotive Innosilicon / Axiado
13:50 – 14:10	An Innovative IR-ECO Technique Enabling Fast Design Convergence for High-End SoC Synopsys / Sanechips	Enabling High-Fidelity SRAM Characterization for Advanced Nodes Primarius Technologies / Primarius Technologies
14:10 – 14:30	Enhancing Thermal Aware Optimization for 3D Heterogeneous Chiplets Integration: A System- Technology Co-Optimization (STCO) Perspective on Spatial-Temporal Temperature Uniformity Synopsys / Witmem	Production-Quality Memory IP Signoff at Scale: A NXP and Siemens EDA Joint Deployment of Solido IP Validation Suite on TSMC Automotive Nodes Siemens EDA / NXP Semiconductors
14:30 – 14:50	LPDDR Memory: Enabling Power-Efficient Performance in AI, Automotive and Data Center Systems Rambus	AI-Powered RF Design Migration Flow for Transition from TSMC’s N6RF+ to N4P Process Node Keysight Technolgies / Synopsys
14:50 – 15:10	Artificial Intelligence in VLSI Physical Design: Practices, Innovations and Trends Cadence Design Systems / Sanechips Technology	M31 ultra-low power foundation IP solution on TSMC N12e Platform: Powering Edge AI and IoT applications M31 Technology / Ambiq Micro
15:10 – 15:30	Coffee Break & Ecosystem Pavilion
15:30 – 15:50	Enabling AI-Optimized Memory Subsystems with LPDDR6/5X and SOCAMM-Based Architectures Cadence Design Systems	Accelerating AI SoC Time-to-Market: NeoFuse OTP as the Silicon-Proven Anchor for PVT Calibration, Memory Repair, and Caliptra-Compliant Root-of-Trust eMemory / ASPEED Technology
15:50 – 16:10	A Scalable PDN Optimization Methodology for Adaptive Multi-Package Automotive MCUs Synopsys / NXP Semiconductors	PCI Express Solutions for HPC/AI Storage: Benefiting from TSMC’s advanced processes Cadence Design Systems / SK hynix
16:10 – 16:30	From Cloud to Physical AI: Edge SoCs on TSMC ‘C’ Nodes Powered by UFS, LPDDR and Die-to-Die Synopsys	TSMC 22ULL MRAM for Automotive MCU Applications Semidrive
16:30	Lucky Draw

Advanced Logic & 3D IC Track	Analog, RF, Specialty Track
Methodology for Fmax-per-Watt Scaling in CPU-Centric Designs Using Advanced EDA and DTCO Techniques Synopsys / Qualcomm Technologies	Breaking the I/O Bottleneck: A Silicon-Proven 4nm M-PHY G5 with Leakage-Optimized Design for High-Bandwidth AI Data Streaming M31 Technology
A Novel Algorithm-Based Approach to Accelerating IR-STA Flow Synopsys / NXP Semiconductors	Accelerate Floorplanning and Rapid Layout Editing with Custom Compiler Smart Floorplanning Synopsys / Mediatek
How Tempus™ PDK Timing Prediction Achieves Timing Signoff Accuracy on TSMC N2P Cadence Design Systems / Broadcom	Integrating Chiptop ESD into Digital Standard Cell Libraries Certus Semiconductor / SRF Technologies / Siemens EDA
Taping out multi-billion-gate, advanced process node SoC with IC Validator Synopsys / Nvidia	TCAD‑Assisted Model Calibration for Reliable SPICE Simulation Across Extreme Temperature Regimes HCL Technologies
A Distributed and Scalable Dynamic Power Integrity Flow from Early Analysis to Sign-off for Large-Scale SerDes Designs Synopsys / Sanechips Technology	Accelerating Memory Cache Verification with AI-Powered Batch Flow Methodology Siemens EDA / Qualcomm
Trust but Verify: Microsoft's IP Validation Methodology Across Design Views and Revisions on TSMC 3nm Siemens EDA / Microsoft	Power-Scalable Multi-Rate eUSB2V2 PHY IP in TSMC N2P M31 Technology
Bridging the Thermal Divide: Empowering ASIC Designers with an Automated Model Generation Toolbox for Thermal-Aware Design HCL Technologies	Mitigating OTP Data Leakage Risks in Advanced SoCs Through Secure Storage Architectures Synopsys
PFSC ESD full chip and 3DIC successful usage Synopsys	Robust PHY Clocking: Silicon Creations in partnership with Synopsys Silicon Creations / Synopsys
Next-Gen Verification: Overcoming ERC and SOFTCHK Challenges for Faster Design Iterations Siemens EDA / SanDisk	AC Noise Characterization Under Dynamic Bias and Its Impact on Circuit Performance Primarius Technologies
M31 high density and ultra-low power STDL on TSMC N3P Platform: Powering Edge AI and AIoT applications M31 Technology
Shift-Left IP Quality Assurance: How Lattice Semiconductor Leverages Solido Crosscheck for FPGA IP Validation on TSMC 16nm FinFET Siemens EDA / Lattice Semiconductors
Automated Architecture-Phase PDN Prototyping Workflow to Advance Multi-Die Designs Synopsys / Mediatek
Scaling up AI Compute, Memory and Connectivity GUC
Warpage Simulation Fitting, Stress Simulation Method and Glass Core Substrate Application of Advanced Package for AI Chips Synopsys / Iluvatar CoreX
Addressing Inter-Die STA Complexity for 3D Multi-Die Designs Synopsys / Arm