|
Time
|
Plenary Session
|
| 08:30 - 09:30 |
Registration & Ecosystem Pavilion |
| 09:30 - 09:40 |
Welcome Remarks |
| 09:40 - 10:00 |
TSMC Keynote |
| 10:00 - 10:30 |
Guest Speech |
| 10:30 - 11:00 |
TSMC Keynote |
| 11:00 – 11:30 |
Coffee Break & Ecosystem Pavilion |
|
TSMC Technical Sessions |
| 11:30 - 12:00 |
TSMC Talk: Synergizing TSMC Angstrom-Scale Technology and AI Computing: Accelerating Silicon and Design Cycle
TSMC
|
TSMC Talk: Scaling AI with Leadership Silicon and Cohesive System Optimization
TSMC
|
|
OIP Partner Technical Talks |
|
Advanced Logic & 3D IC Track |
Analog, RF, Specialty Track |
| 12:00 - 12:20 |
Scaling AI Data Center’s Infrastructure: Protocol Agnostic Physical Design for Scale-Up using 224G SerDes
Alchip Technologies / Synopsys
|
AI-Accelerated Surrogate Modeling for Rapid RFIC/MMIC Design Validation
Keysight Technolgies
|
| 12:20 – 13:30 |
Lunch & Ecosystem Pavilion |
| 13:30 – 13:50 |
ATPG Solutions for Small-delay Defects -- Path-Delay vs Timing-Aware
Siemens EDA / AMD
|
Driving Next Gen Memory Interfaces: LPDDR6/5X combo subsystem for High Bandwidth, Low Latency with Optimum Data Traffic with CPU/GPU/XPU, in Applications such as AI, Cyber security, Datacenter, and Automotive
Innosilicon / Axiado
|
| 13:50 – 14:10 |
An Innovative IR-ECO Technique Enabling Fast Design Convergence for High-End SoC
Synopsys / Sanechips
|
Enabling High-Fidelity SRAM Characterization for Advanced Nodes
Primarius Technologies / Primarius Technologies
|
| 14:10 – 14:30 |
Enhancing Thermal Aware Optimization for 3D Heterogeneous Chiplets Integration: A System- Technology Co-Optimization (STCO) Perspective on Spatial-Temporal Temperature Uniformity
Synopsys / Witmem
|
Production-Quality Memory IP Signoff at Scale: A NXP and Siemens EDA Joint Deployment of Solido IP Validation Suite on TSMC Automotive Nodes
Siemens EDA / NXP Semiconductors
|
| 14:30 – 14:50 |
LPDDR Memory: Enabling Power-Efficient Performance in AI, Automotive and Data Center Systems
Rambus
|
AI-Powered RF Design Migration Flow for Transition from TSMC’s N6RF+ to N4P Process Node
Keysight Technolgies / Synopsys
|
| 14:50 – 15:10 |
Artificial Intelligence in VLSI Physical Design: Practices, Innovations and Trends
Cadence Design Systems / Sanechips Technology
|
M31 ultra-low power foundation IP solution on TSMC N12e Platform: Powering Edge AI and IoT applications
M31 Technology / Ambiq Micro
|
| 15:10 – 15:30 |
Coffee Break & Ecosystem Pavilion |
| 15:30 – 15:50 |
Enabling AI-Optimized Memory Subsystems with LPDDR6/5X and SOCAMM-Based Architectures
Cadence Design Systems
|
Accelerating AI SoC Time-to-Market: NeoFuse OTP as the Silicon-Proven Anchor for PVT Calibration, Memory Repair, and Caliptra-Compliant Root-of-Trust
eMemory / ASPEED Technology
|
| 15:50 – 16:10 |
A Scalable PDN Optimization Methodology for Adaptive Multi-Package Automotive MCUs
Synopsys / NXP Semiconductors
|
PCI Express Solutions for HPC/AI Storage: Benefiting from TSMC’s advanced processes
Cadence Design Systems / SK hynix
|
| 16:10 – 16:30 |
From Cloud to Physical AI: Edge SoCs on TSMC ‘C’ Nodes Powered by UFS, LPDDR and Die-to-Die
Synopsys
|
TSMC 22ULL MRAM for Automotive MCU Applications
Semidrive
|
| 16:30 |
Lucky Draw |
