Agenda：Online Event

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Join the 2026 TSMC Open Innovation Platform Ecosystem Forum and learn from OIP partners how to leverage their technology for your design challenges!

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Date: Tuesday, December 1, 2026

Plenary Session
Welcome & Ecosystem Pavilion
Opening Remarks
TSMC Keynote & Guest Speech

Included All In-Person Papers

Advanced Logic & 3D IC Track

Methodology for Fmax-per-Watt Scaling in CPU-Centric Designs Using Advanced EDA and DTCO Techniques

Synopsys / Qualcomm Technologies

A Novel Algorithm-Based Approach to Accelerating IR-STA Flow

Synopsys / NXP Semiconductors

How Tempus™ PDK Timing Prediction Achieves Timing Signoff Accuracy on TSMC N2P

Cadence Design Systems / Broadcom

Taping out multi-billion-gate, advanced process node SoC with IC Validator

Synopsys / Nvidia

A Distributed and Scalable Dynamic Power Integrity Flow from Early Analysis to Sign-off for Large-Scale SerDes Designs

Synopsys / Sanechips Technology

Trust but Verify: Microsoft's IP Validation Methodology Across Design Views and Revisions on TSMC 3nm

Siemens EDA / Microsoft

Bridging the Thermal Divide: Empowering ASIC Designers with an Automated Model Generation Toolbox for Thermal-Aware Design

HCL Technologies

PFSC ESD full chip and 3DIC successful usage

Synopsys

Next-Gen Verification: Overcoming ERC and SOFTCHK Challenges for Faster Design Iterations

Siemens EDA / SanDisk

M31 high density and ultra-low power STDL on TSMC N3P Platform: Powering Edge AI and AIoT applications

M31 Technology

Shift-Left IP Quality Assurance: How Lattice Semiconductor Leverages Solido Crosscheck for FPGA IP Validation on TSMC 16nm FinFET

Siemens EDA / Lattice Semiconductors

Automated Architecture-Phase PDN Prototyping Workflow to Advance Multi-Die Designs

Synopsys / Mediatek

Scaling up AI Compute, Memory and Connectivity

GUC

Warpage Simulation Fitting, Stress Simulation Method and Glass Core Substrate Application of Advanced Package for AI Chips

Synopsys / Iluvatar CoreX

Addressing Inter-Die STA Complexity for 3D Multi-Die Designs

Synopsys / Arm
Analog, RF, Specialty Track

Breaking the I/O Bottleneck: A Silicon-Proven 4nm M-PHY G5 with Leakage-Optimized Design for High-Bandwidth AI Data Streaming

M31 Technology

Accelerate Floorplanning and Rapid Layout Editing with Custom Compiler Smart Floorplanning

Synopsys / Mediatek

Integrating Chiptop ESD into Digital Standard Cell Libraries

Certus Semiconductor / SRF Technologies / Siemens EDA

TCAD‑Assisted Model Calibration for Reliable SPICE Simulation Across Extreme Temperature Regimes

HCL Technologies

Accelerating Memory Cache Verification with AI-Powered Batch Flow Methodology

Siemens EDA / Qualcomm

Power-Scalable Multi-Rate eUSB2V2 PHY IP in TSMC N2P

M31 Technology

Mitigating OTP Data Leakage Risks in Advanced SoCs Through Secure Storage Architectures

Synopsys

Robust PHY Clocking: Silicon Creations in partnership with Synopsys

Silicon Creations / Synopsys

AC Noise Characterization Under Dynamic Bias and Its Impact on Circuit Performance

Primarius Technologies

*The agenda is subject to change by TSMC.

Legal Notice

TSMC is not responsible for the content, accuracy, or reliability of any of the presentations at the TSMC Open Innovation Platform Ecosystem Forum. Furthermore, posting the presentation abstracts on TSMC's corporate website does not constitute an endorsement of the content of those presentations by TSMC. Any liability arising from the contents of any of the presentations is the responsibility of the presenter itself, and not TSMC.

The views expressed in the presentations made at this event are those of the speaker and are not necessarily those of TSMC.