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Analog, RF, Specialty Track 15:30 – 15:50
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PCI Express Solutions for HPC/AI Storage: Benefiting from TSMC’s advanced processes
Cadence Design Systems / SK hynix
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Abstract
This subsystem-centric, ecosystem-driven approach delivers:
• Optimized robust PHY performance achieved over PVT for TX jitter and RX JTOL with margins and full compliance with PCIe specifications. Across advanced process nodes and challenging channel environments
• Feature-complete, standards-ready PCIe controllers supporting advanced storage use cases
• Robust, production-proven PCIe subsystems with improved signal integrity, power efficiency, and reliability
• Faster time-to-market through reduced integration risk and system-level validation
• Cost-effective scaling of PCIe product portfolios across HPC, AI, and storage applications
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Legal Notice
TSMC is not responsible for the content, accuracy, or reliability of any of the presentations at the TSMC Open Innovation Platform Ecosystem Forum. Furthermore, posting the presentation abstracts on TSMC's corporate website does not constitute an endorsement of the content of those presentations by TSMC. Any liability arising from the contents of any of the presentations is the responsibility of the presenter itself, and not TSMC.
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