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3D IC Track 14:30 – 14:50
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Scaling up AI Compute, Memory and Connectivity
GUC
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Abstract
• GUC’s 3D interface, GLink-3D, achieves an interconnect density of 16 TB/s/mm² between stacked dies, with power efficiency of 0.03 pJ/bit and latency below 1 ns, it has been silicon-proven in TSMC N5, N3, and N2 process nodes
• SoIC-X power delivery methodology utilizing through-silicon vias (TSVs) in the bottom die, supporting power densities of 5 W/mm² and above
• Accurate thermal modeling of SoIC-X structures using 3DBlox abstraction at early design stages to avoid costly interactions at later stages
• Designed GUC’s DRAM-on-Logic Memory Controller, supporting multiple DRAM banks with high bandwidth and area efficiency
• Silicon results of GUC’s Integrated Voltage Regulator (IVR) with patent-pending Resistive Transient Assist (RTA) circuit for fast response to xPU workload changes
• GUC shares its COUPE design experience, addressing power delivery, thermal management and integration of optical engines within multi-reticle xPU systems
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