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3D IC Track 13:50 – 14:10
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Scaling AI Data Center’s Infrastructure: Protocol Agnostic Physical Design for Scale-Up using 224G SerDes
Alchip Technologies / Synopsys
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Abstract
Using this collaborative methodology, Alchip and Synopsys achieve chip‑to‑chip interconnect bandwidth density exceeding 1.2 Tbps/mm, approaching current theoretical physical limits. These results demonstrate the feasibility of ultra‑high‑density 224G scale‑up interconnect implementations within realistic die edge and package constraints.
The approach benefits customers developing AI accelerators and high‑performance networking ASICs for data center scale‑up applications, where maximizing bandwidth per millimeter directly impacts system throughput and scalability. By addressing escape routing and SI/PI constraints early in the physical design process, the methodology reduces integration risk and establishes a clear technical path for scaling from 224G to next‑generation 448G interconnect technologies.
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