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3D IC Track
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A Robust EDA Framework for Silicon Photonic Design Integration: Connectivity and Signoff in PDIE
Cadence Design Systems
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Abstract
CDNS works with customers with the benefit observed:
Improved Design Productivity: Eliminates time-consuming manual fixes, reducing engineering effort and turnaround time for PDIE integration.
Enhanced Flow Robustness and Predictability: Provides deterministic connectivity generation, enabling consistent results across designs and reducing iteration cycles.
Higher Signoff Confidence: Built-in layout-aware validation reduces late-stage DRC/LVS issues, improving overall design quality and tapeout readiness.
Scalability to Complex Integration Scenarios: Supports advanced heterogeneous integration with diverse bump configurations and incomplete design information.
Reduced Risk in Production Flows: Minimizes connectivity-related failures and downstream violations, lowering risk for high-volume manufacturing deployment.
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