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Advanced Logic Track
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A Novel Algorithm-Based Approach to Accelerating IR-STA Flow
Synopsys / NXP Semiconductors
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Abstract
Experimental results across multiple IR-run modes demonstrate:
• up to 63% runtime reduction compared to conventional IR-STA flow.
• with negligible computational overhead and minimal error (MAE < 0.1ps).
• process- and design-independent.
This methodology enables faster design iterations, improving PDN and timing closure efficiency in advanced chip designs. Meanwhile, this approach offers strong portability and potential applicability to other STA-related scenarios.
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