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3D IC Track 13:30 – 13:50
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Efficient, scalable methodology for reliability and ESD verification of complex 3D IC CoWoS systems
Siemens EDA / Marvell
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Abstract
This presentation introduces a new approach for package-level connectivity and ESD verification in multi-die, multi-foundry, and multi-technology systems that also include stacked HBM memories and passive elements in the IPD module. To our knowledge, this package-level ESD and connectivity verification checker is the first of its kind in the semiconductor industry. The work addresses a critical need by helping ensure that complex CoWoS-based system-in-package designs are correct in both connectivity and ESD robustness, improving the likelihood of first-pass success.
Its impact is substantial because even a single package-level error can require a respin with a cycle time of several months to a year. Such delays can lead to lost technology leadership, missed design wins, and reduced customer confidence in a highly competitive semiconductor market. By enabling earlier and more comprehensive verification, this methodology helps reduce costly late-stage issues and supports more reliable product execution.
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