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Advanced Logic Track
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Taping out multi-billion-gate, advanced process node SoC with IC Validator
Synopsys / Nvidia
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Abstract
NVIDIA achieved up to a 20X TAT improvement for small cell runtimes at leading edge nodes. For full chip SoC verification, NVIDIA completed a flagship advanced node, multi-billion gate design tape out project with physical verification signoff in under 24-hours. Ongoing collaboration with Synopsys, along with optimizations for Grace class platforms, continues to deliver additional performance gains, enabling NVIDIA to rely on IC Validator for advanced node physical verification signoff.
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