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Advanced Logic Track 14:50 – 15:10
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Methodology for Fmax-per-Watt Scaling in CPU-Centric Designs Using Advanced EDA and DTCO Techniques
Synopsys / Qualcomm Technologies
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Abstract
A systematic PPA optimization methodology was developed for advanced GAA-based technology nodes targeting CPU designs, combining variable-row implementations (4-5% Fmax improvement), BEOL-focused interconnect tuning, and QTI-enriched libraries (4-5% Fmax improvement and 2-4% PPW improvement). The approach successfully met Fmax-per-watt targets while maintaining favorable power-performance tradeoffs on one of the Nanoflex technologies.
These recipes were designed for direct adoption into production flow testing, enabling broader deployment across design teams with minimal disruption.
Learnings from this work—particularly around metal-stack and interconnect optimization—are being extended to newer nodes, establishing a foundation for continued PPW-driven design enablement and accelerating ramp-up on next-generation processes.
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