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Advanced Logic Track 16:10 – 16:30
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How Tempus™ PDK Timing Prediction Achieves Timing Signoff Accuracy on TSMC N2P
Cadence Design Systems / Broadcom
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Abstract
Measured Technical Results
The Silicon Prediction flow delivers quantifiable timing accuracy improvements across every validated corner and node combination. At the most critical ultra-low-voltage corners — where PDK-to-PDK timing divergence is greatest and signoff risk is highest — the results are particularly compelling:
• 5–10× reduction in median timing error at stressed ULV corners, where prediction matters most for early design decisions.
• 3FFE ff0450-40 (ULV): Median setup error reduced from +9.94% to +1.56%; worst-case error reduced from +25.49% to +8.38% — an 84% improvement in median accuracy and a 67% improvement in worst-case accuracy.
• 2GAAP ff0500-40 (ULV): Median setup error reduced from +14.86% to +2.39%; worst-case error reduced from +29.21% to +16.01% — an 84% improvement in median accuracy and a 45% improvement in worst-case accuracy.
• 20–35% reduction in slack distribution range at stressed corners, tightening the spread of timing uncertainty across paths and giving designers a more predictable signoff margin picture.
• At well-correlated corners (3FFE ff0760-40, ss0500125), near-zero correction is applied automatically, confirming the flow introduces zero artificial pessimism where none is warranted.
• Final prediction accuracy lands within ~1–2% median and below ~10% worst-case of full re-characterization across all 7 PVT corners and 5 Vth flavors — with a single unified fitting recipe and no per-corner tuning.
Schedule & Business Impact
The most transformative impact is on design cycle time. Full library re-characterization typically consumes weeks of compute time and engineering coordination, creating a hard bottleneck between PDK release and the start of meaningful timing closure work. Silicon Prediction compresses this to hours, unlocking several downstream benefits:
• Weeks reclaimed per PDK revision cycle, directly expandable into additional design iterations, more thorough timing closure, or earlier tapeout readiness.
• Earlier risk identification: Design teams can assess timing risk, identify critical path vulnerabilities, and initiate ECO cycles immediately after a PDK drop rather than waiting for full characterization — potentially surfacing and resolving timing violations weeks earlier in the project timeline.
• Tighter signoff margins: With prediction accuracy well below 10% worst-case, teams can confidently set signoff guard-bands based on predicted timing rather than conservative worst-case assumptions, reducing over-margining and its associated area and power penalties.
Who Benefits
• SoC and ASIC design teams at leading semiconductor companies working on advanced TSMC nodes (3FFE, 2GAAP and beyond) who face repeated PDK revision cycles throughout the design lifecycle.
• Hyperscaler and networking chip designers — the BRCM standard cell library validation directly signals relevance to high-volume, performance-critical silicon in data center, networking, and AI accelerator applications.
• Any design team using Cadence Liberate and Tempus in their existing signoff flow, for whom adoption requires no new infrastructure investment.
• Physical design and timing closure teams under aggressive tapeout schedules at 3nm-class nodes where PDK maturity evolves rapidly and revision frequency is high.
Summary Value Proposition
Metric Baseline With Silicon Prediction
Median timing error (ULV) ~10–15% ~1–2%
Worst-case timing error (ULV) ~25–29% ~8–16%
Library update turnaround Weeks Hours
Per-corner tuning required Yes None
Artificial pessimism at stable corners Risk present Zero
Silicon Prediction does not replace full re-characterization at tapeout — but it fundamentally changes what design teams can accomplish between PDK releases, compressing schedule risk, improving timing confidence, and enabling faster, more informed decisions throughout the advanced node design lifecycle.
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Legal Notice
TSMC is not responsible for the content, accuracy, or reliability of any of the presentations at the TSMC Open Innovation Platform Ecosystem Forum. Furthermore, posting the presentation abstracts on TSMC's corporate website does not constitute an endorsement of the content of those presentations by TSMC. Any liability arising from the contents of any of the presentations is the responsibility of the presenter itself, and not TSMC.
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