 |
|
Analog, RF, Specialty Track
|
 |
Leveraging Cloud-Scale Infrastructure to Accelerate Silicon Tape-Outs using ARM core Graviton processors.
Siemens EDA / Amazon
|
 |
Abstract
Key results include a 70% reduction in physical verification DRC compute runtime through distributed scaling and the utilization of Amazon EC2 on-demand ARM core instances, alongside a dramatic improvement in time-to-market for successive generations of Graviton CPUs, Trainium, and Inferentia accelerators. This study demonstrates that immediate access to the latest compute hardware enables a continuous scaling to optimize turnaround times to meet tapeout schedule requirements.
|
|
Legal Notice
TSMC is not responsible for the content, accuracy, or reliability of any of the presentations at the TSMC Open Innovation Platform Ecosystem Forum. Furthermore, posting the presentation abstracts on TSMC's corporate website does not constitute an endorsement of the content of those presentations by TSMC. Any liability arising from the contents of any of the presentations is the responsibility of the presenter itself, and not TSMC.
|
|
