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3D IC Track 15:50 – 16:10
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Hierarchical design planning and verification for CoWoS-L technology: an incremental methodology
Siemens EDA / ARM
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Abstract
The paper demonstrates how this i3Di-based flow supports an innovative 'incremental' methodology, allowing physical verification to be executed even before the full assembly is complete (allowing faster design and quicker tapeout). With its complete knowledge of the CoWoS-L system, the i3Di cockpit intelligently partitions the system and exports tailored runsets for specific tasks, such as standalone LSI verification, single tile verification, and ultimately, full CoWoS-L system (e.g., two tiles + LSI + package) physical verification. Furthermore, the paper showcases the utilization of the TSMC 3Dblox methodology, enabling designers to more effectively leverage TSMC's 3DFabric ecosystem
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