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3D IC Track
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COUPE‑Enabled Co‑Packaged Optics through ASIC and Photonic Interconnect Co‑Design
Alphawave Semi / Lightmatter
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Abstract
The proposed COUPE‑enabled CPO architecture targets next‑generation AI accelerators and switching platforms that require extreme bandwidth density and improved energy efficiency. Primary beneficiaries include hyperscale and enterprise AI infrastructure designers deploying multi‑die accelerators and optical scale‑up networks.
By tightly integrating ASIC, photonic, and packaging design, this approach enables:
Higher aggregate bandwidth scaling beyond 100 Tb/s
Improved power efficiency through reduced electrical reach and optimized PHY placement
A manufacturable path using standardized interfaces and silicon‑proven IP
Faster system bring‑up through co‑optimized electrical‑optical partitioning
Overall, this work demonstrates a practical, system‑level foundation for deploying co‑packaged optics in production AI platforms, accelerating the transition toward scalable, power‑efficient optical I/O architectures.
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