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Advanced Logic Track 14:10 – 14:30
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Accelerating Physical Verification with Agentic AI DRC Fixing
Siemens EDA / Google
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Abstract
For many categories of design rule checks, this approach enables full automation of the debug-and-fix tasks that previously required substantial manual intervention, addressing over 90% of violations in those classes. Tasks that traditionally require hours of engineering time can now be reduced to minutes of reviewing and approving AI proposed fixes. When applied across the repeated block- and SoC-level verification cycles characteristic of advanced designs, these gains translate into meaningful reductions in the duration of the final tape-out phases, where even small schedule slips can carry significant economic impact at advanced process nodes. We also present feedback from Google on their experience evaluating this capability.
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