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OIP Partner Technical Session |
|
Advanced Logic Track |
3D IC Track |
Analog, RF, Specialty Track |
| 11:15 – 11:35 |
Taping out multi-billion-gate, advanced process node SoC with IC Validator
Synopsys / Nvidia
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From Design to Mass Production: GUC and FuriosaAI’s Joint Collaboration on RNGD
GUC / FuriosaAI
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Datacenter-Scale CPU Power Management using Integrated Power and Clocking in N3/N2 SoCs
Analog Bits / Arm
|
| 11:35 – 11:55 |
Protecting the Bits that Power AI
EPFL
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Enabling AI-Optimized Memory Subsystems with LPDDR6/5X and SOCAMM-Based Architectures
Cadence Design Systems
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AI-Powered RF Design Migration Flow for Transition from TSMC’s N6RF+ to N4P Process Node
Keysight Technolgies / Synopsys
|
| 11:55 – 13:00 |
Lunch & Ecosystem Pavilion |
| 13:00 – 13:20 |
A Novel Algorithm-Based Approach to Accelerating IR-STA Flow
Synopsys / NXP Semiconductors
|
Designing with CoWoS S, CoWoS R and CoWoS L: package technology selection and co design for next generation heterogeneous systems
IMEC
|
Parasitic-Aware Analog Layout Exploration and Optimization in Advanced FinFET Technologies for Robust Analog Design
Cadence Design Systems / Infineon Technologies AG / Cadence
|
| 13:20 – 13:40 |
Methodology for Fmax-per-Watt Scaling in CPU-Centric Designs Using Advanced EDA and DTCO Techniques
Synopsys / Qualcomm Technologies
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COUPE‑Enabled Co‑Packaged Optics through ASIC and Photonic Interconnect Co‑Design
Alphawave Semi / Lightmatter
|
Production-Quality Memory IP Signoff at Scale: A NXP and Siemens EDA Joint Deployment of Solido IP Validation Suite on TSMC Automotive Nodes
Siemens EDA / NXP Semiconductors
|
| 13:40 – 14:00 |
How Tempus™ PDK Timing Prediction Achieves Timing Signoff Accuracy on TSMC N2P
Cadence Design Systems / Broadcom
|
Scaling AI Data Center’s Infrastructure: Protocol Agnostic Physical Design for Scale-Up using 224G SerDes
Alchip Technologies / Synopsys
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TSMC 22ULL MRAM for Automotive MCU Applications
Semidrive
|
| 14:00 – 14:20 |
Accelerating Physical Verification with Agentic AI DRC Fixing
Siemens EDA / Google
|
A Scalable PDN Optimization Methodology for Adaptive Multi-Package Automotive MCUs
Synopsys / NXP Semiconductors
|
M31 ultra-low power foundation IP solution on TSMC N12e Platform: Powering Edge AI and IoT applications
M31 Technology / Ambiq Micro
|
| 14:20 – 14:40 |
ETHEREAL: A 28nm Low-latency Event-Driven Graph-Neural-Network Processor Chip for Real-time High-resolution Vision at the Edge.
Delft University of Technology
|
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Accelerating Time to Market: Variation Sensitive Cell Detection and Repair using AI
Siemens EDA / NXP
|
| 14:40 – 15:00 |
Coffee Break & Ecosystem Pavilion |
